1. Field of the Invention
The present invention relates to a semiconductor memory device such as a dynamic random access memory (DRAM) device including a dual word line configuration having main word lines and sub word lines.
2. Description of the Related Art
In a prior art DRAM device incorporating redundancy memory cells, if a defective memory cell is found, an address indicating the defective memory cell is written into a redundancy decoder by laser trimming or the like and, and simultaneously, a fuse within a sense amplifier connected to the defective memory cell is melted. Thus, no direct current (DC) path is generated in the sense amplifier connected to the defective memory cell in a sense mode, to thereby reduce the power dissipation (see JP-A-HEI3-225851). This will be explained later in detail.
On the other hand, a dual word line configuration having main word lines and sub word lines has been adopted for DRAM devices (see Tadahiko Sugibayashi et al., "A 30 ns 256 Mb DRAM with Multi-Divided Array Structure", Digest of IEEE International Solid-State Circuits Conference, pp. 50-51, 1993). Since the main word lines and the sub word lines are separately driven, the power dissipation can be reduced. Also, the pitch of the main word lines can be not strict, which is helpful in the manufacutre of large scale devices. This will also be explained later in detail.
In the above-described dual word line type DRAM device, a voltage at one of the main word lines is always different from a voltage at the other. Therefore, if the two main word lines are short-circuited, a current always flows therethrough, which increases the power dissipation.
If fuses are forcibly introduced into the main word lines of the dual word line configuration, the melting of the fuses causes the main word lines to be in a high impedance state, so that the operation of sub word decoders connected to the main word lines is unstable.